From 6df9fc75d2d39f33a39b424d37cc6eb5b67070dd Mon Sep 17 00:00:00 2001 From: Philip Rebohle Date: Tue, 19 Dec 2017 00:45:31 +0100 Subject: [PATCH] [dxbc] Implemented some new bit-wise logical instructions --- src/dxbc/dxbc_compiler.cpp | 36 ++++++++++++++++++++--- src/dxbc/dxbc_defs.cpp | 23 ++++++++++++--- src/spirv/spirv_module.cpp | 58 ++++++++++++++++++++++++++++++++++++++ src/spirv/spirv_module.h | 19 +++++++++++++ 4 files changed, 128 insertions(+), 8 deletions(-) diff --git a/src/dxbc/dxbc_compiler.cpp b/src/dxbc/dxbc_compiler.cpp index 7e679a13..88f184e1 100644 --- a/src/dxbc/dxbc_compiler.cpp +++ b/src/dxbc/dxbc_compiler.cpp @@ -622,6 +622,14 @@ namespace dxvk { const uint32_t typeId = getVectorTypeId(dst.type); switch (ins.op) { + ///////////////////// + // Move instructions + case DxbcOpcode::Mov: + dst.id = src.at(0).id; + break; + + ///////////////////////////////////// + // ALU operations on float32 numbers case DxbcOpcode::Add: dst.id = m_module.opFAdd(typeId, src.at(0).id, src.at(1).id); @@ -662,10 +670,6 @@ namespace dxvk { src.at(0).id, src.at(1).id); break; - case DxbcOpcode::Mov: - dst.id = src.at(0).id; - break; - case DxbcOpcode::Sqrt: dst.id = m_module.opSqrt( typeId, src.at(0).id); @@ -676,6 +680,8 @@ namespace dxvk { typeId, src.at(0).id); break; + ///////////////////////////////////// + // ALU operations on signed integers case DxbcOpcode::IAdd: dst.id = m_module.opIAdd(typeId, src.at(0).id, src.at(1).id); @@ -702,7 +708,29 @@ namespace dxvk { dst.id = m_module.opSNegate( typeId, src.at(0).id); break; + + /////////////////////////////////////// + // Bit operations on unsigned integers + case DxbcOpcode::And: + dst.id = m_module.opBitwiseAnd(typeId, + src.at(0).id, src.at(1).id); + break; + case DxbcOpcode::Not: + dst.id = m_module.opNot( + typeId, src.at(0).id); + break; + + case DxbcOpcode::Or: + dst.id = m_module.opBitwiseOr(typeId, + src.at(0).id, src.at(1).id); + break; + + case DxbcOpcode::Xor: + dst.id = m_module.opBitwiseXor(typeId, + src.at(0).id, src.at(1).id); + break; + default: Logger::warn(str::format( "DxbcCompiler: Unhandled instruction: ", diff --git a/src/dxbc/dxbc_defs.cpp b/src/dxbc/dxbc_defs.cpp index 3709cfa3..9009bce4 100644 --- a/src/dxbc/dxbc_defs.cpp +++ b/src/dxbc/dxbc_defs.cpp @@ -10,7 +10,11 @@ namespace dxvk { { DxbcOperandKind::SrcReg, DxbcScalarType::Float32 }, } }, /* And */ - { }, + { 3, DxbcInstClass::VectorAlu, { + { DxbcOperandKind::DstReg, DxbcScalarType::Uint32 }, + { DxbcOperandKind::SrcReg, DxbcScalarType::Uint32 }, + { DxbcOperandKind::SrcReg, DxbcScalarType::Uint32 }, + } }, /* Break */ { 0, DxbcInstClass::ControlFlow }, /* Breakc */ @@ -242,9 +246,16 @@ namespace dxvk { /* Nop */ { }, /* Not */ - { }, + { 2, DxbcInstClass::VectorAlu, { + { DxbcOperandKind::DstReg, DxbcScalarType::Uint32 }, + { DxbcOperandKind::SrcReg, DxbcScalarType::Uint32 }, + } }, /* Or */ - { }, + { 3, DxbcInstClass::VectorAlu, { + { DxbcOperandKind::DstReg, DxbcScalarType::Uint32 }, + { DxbcOperandKind::SrcReg, DxbcScalarType::Uint32 }, + { DxbcOperandKind::SrcReg, DxbcScalarType::Uint32 }, + } }, /* ResInfo */ { }, /* Ret */ @@ -325,7 +336,11 @@ namespace dxvk { /* UtoF */ { }, /* Xor */ - { }, + { 3, DxbcInstClass::VectorAlu, { + { DxbcOperandKind::DstReg, DxbcScalarType::Uint32 }, + { DxbcOperandKind::SrcReg, DxbcScalarType::Uint32 }, + { DxbcOperandKind::SrcReg, DxbcScalarType::Uint32 }, + } }, /* DclResource */ { 2, DxbcInstClass::Declaration, { { DxbcOperandKind::DstReg, DxbcScalarType::Float32 }, diff --git a/src/spirv/spirv_module.cpp b/src/spirv/spirv_module.cpp index f856642b..163a6c49 100644 --- a/src/spirv/spirv_module.cpp +++ b/src/spirv/spirv_module.cpp @@ -581,6 +581,64 @@ namespace dxvk { } + uint32_t SpirvModule::opBitwiseAnd( + uint32_t resultType, + uint32_t operand1, + uint32_t operand2) { + uint32_t resultId = this->allocateId(); + + m_code.putIns (spv::OpBitwiseAnd, 5); + m_code.putWord(resultType); + m_code.putWord(resultId); + m_code.putWord(operand1); + m_code.putWord(operand2); + return resultId; + } + + + uint32_t SpirvModule::opBitwiseOr( + uint32_t resultType, + uint32_t operand1, + uint32_t operand2) { + uint32_t resultId = this->allocateId(); + + m_code.putIns (spv::OpBitwiseOr, 5); + m_code.putWord(resultType); + m_code.putWord(resultId); + m_code.putWord(operand1); + m_code.putWord(operand2); + return resultId; + } + + + uint32_t SpirvModule::opBitwiseXor( + uint32_t resultType, + uint32_t operand1, + uint32_t operand2) { + uint32_t resultId = this->allocateId(); + + m_code.putIns (spv::OpBitwiseXor, 5); + m_code.putWord(resultType); + m_code.putWord(resultId); + m_code.putWord(operand1); + m_code.putWord(operand2); + return resultId; + } + + + uint32_t SpirvModule::opNot( + uint32_t resultType, + uint32_t operand) { + uint32_t resultId = this->allocateId(); + + m_code.putIns (spv::OpNot, 4); + m_code.putWord(resultType); + m_code.putWord(resultId); + m_code.putWord(operand); + return resultId; + } + + uint32_t SpirvModule::opCompositeConstruct( uint32_t resultType, uint32_t valueCount, diff --git a/src/spirv/spirv_module.h b/src/spirv/spirv_module.h index f87160df..64866651 100644 --- a/src/spirv/spirv_module.h +++ b/src/spirv/spirv_module.h @@ -216,6 +216,25 @@ namespace dxvk { uint32_t resultType, uint32_t operand); + uint32_t opBitwiseAnd( + uint32_t resultType, + uint32_t operand1, + uint32_t operand2); + + uint32_t opBitwiseOr( + uint32_t resultType, + uint32_t operand1, + uint32_t operand2); + + uint32_t opBitwiseXor( + uint32_t resultType, + uint32_t operand1, + uint32_t operand2); + + uint32_t opNot( + uint32_t resultType, + uint32_t operand); + uint32_t opCompositeConstruct( uint32_t resultType, uint32_t valueCount,